HCL Technologies Limited is seeking an experienced verification engineer to lead and contribute to the verification of multiple ASIC blocks using UVM-based settings. You will develop sequences, tests, and debug strategies while driving coverage closure and end-to-end verification across assigned blocks.
The role requires solid SystemVerilog/UVM skills and hands-on experience with PCIe, UCIe 2.0, and Ethernet protocols.
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📌 Senior Asic Verification Lead Systemverilog/uvm, Ethernet Toronto (Canada)
🏢 HCL Technologies
📍 Canada
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