Senior Asic Design Engineer – Verilog/Ppa Expert - $150,000 - $250,000 A Year (Varennes)

Senior Asic Design Engineer – Verilog/Ppa Expert - $150,000 - $250,000 A Year (Varennes)

06 Aug
|
Semiconductor Start-Up
|
Varennes

06 Aug

Semiconductor Start-Up

Varennes

Seeking an ASIC Design Engineer with Verilog/PPA expertise for optical transceiver development. Responsibilities include digital circuit design, synthesis, and timing analysis.

📌 Senior Asic Design Engineer – Verilog/Ppa Expert - $150,000 - $250,000 A Year (Varennes)
🏢 Semiconductor Start-Up
📍 Varennes

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