Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Varennes)

Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Varennes)

06 Aug
|
LanceSoft
|
Varennes

06 Aug

LanceSoft

Varennes

Seeking an RTL/FPGA Design Engineer with 15+ years experience. Requires Verilog and System Verilog skills. Contract position.

📌 Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Varennes)
🏢 LanceSoft
📍 Varennes

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