Senior Rtl Design Engineer — Verilog, Synthesis & Cdc - C$77,000 - C$120,000 A Year (Toronto)

Senior Rtl Design Engineer — Verilog, Synthesis & Cdc - C$77,000 - C$120,000 A Year (Toronto)

06 Aug
|
Wipro
|
Toronto

06 Aug

Wipro

Toronto

Experienced digital designer needed to support and debug RTL designs. Requires expertise in Verilog and knowledge of CDC tools. Market-competitive salary and flexible work model.

📌 Senior Rtl Design Engineer — Verilog, Synthesis & Cdc - C$77,000 - C$120,000 A Year (Toronto)
🏢 Wipro
📍 Toronto

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