Asic Verification Engineer — Systemverilog/Uvm Expert - $150,000 - $250,000 A Year (Boucherville)

Asic Verification Engineer — Systemverilog/Uvm Expert - $150,000 - $250,000 A Year (Boucherville)

06 Aug
|
Tech Start-Up
|
Boucherville

06 Aug

Tech Start-Up

Boucherville

Seeking an experienced ASIC Verification Engineer to develop and implement verification plans, design testbenches, and execute test cases for complex ASIC designs in the semiconductor industry.

📌 Asic Verification Engineer — Systemverilog/Uvm Expert - $150,000 - $250,000 A Year (Boucherville)
🏢 Tech Start-Up
📍 Boucherville

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