Asic Verification Engineer — Systemverilog/Uvm Expert - $150,000 - $250,000 A Year (Varennes)

Asic Verification Engineer — Systemverilog/Uvm Expert - $150,000 - $250,000 A Year (Varennes)

06 Aug
|
CELERO COMMUNICATIONS
|
Varennes

06 Aug

CELERO COMMUNICATIONS

Varennes

Seeking an experienced ASIC Verification Engineer for a tech start-up to create verification plans, testbenches, and test cases for complex ASIC designs.

📌 Asic Verification Engineer — Systemverilog/Uvm Expert - $150,000 - $250,000 A Year (Varennes)
🏢 CELERO COMMUNICATIONS
📍 Varennes

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