06 Aug
|
Global Semiconductor Leader
|
Winnipeg
06 Aug
Global Semiconductor Leader
Winnipeg
A global semiconductor leader seeks a seasoned engineering leader to advance analog and mixed-signal IP development. You will define methodologies, enhance workflow, and provide technical leadership to ensure high-quality design outcomes. With over 5 years of experience required, candidates should have expertise in analog/mixed-signal layout and familiarity with industry tools like Synopsys Custom Compiler and Cadence Virtuoso. You'll mentor junior engineers while collaborating with interdisciplinary teams to drive creative solutions in a fast-paced environment.#J-18808-Ljbffr
📌 Leading Analog Layout At Infosys (Winnipeg)
🏢 Global Semiconductor Leader
📍 Winnipeg