Drive ASIC design verification at HCLTech! Looking for a Senior Technical Architect to lead verification of ASIC design blocks, develop UVM environments, and collaborate with clients remotely.At HCLTech, you'll own the verification for several design blocks, utilizing your SystemVerilog/UVM expertise in a client-facing role. Your responsibilities will include designing verification environments, executing test sequences, and ensuring coverage closure. Support your team while enhancing your skills in cutting-edge technology and leading impactful solutions.Key Responsibilities:
- Lead verification for 4-5 ASIC design blocks
- Develop UVM-based environments and test sequences
- Execute tests, debugging, and troubleshoot issues
- Drive coverage closure for project deliverables
- Collaborate with customers in EST timezoneRequirements:
- Strong experience in SystemVerilog and UVM
- Expertise with protocols like PCIe, UCIe 2.0, and Ethernet
- Ability to independently own verification deliverables
- Background in developing end-to-end verification processes
- Knowledge of Ethernet and design verification techniquesLeverage your technical expertise in a rewarding and agile environment at HCLTech!#J-18808-Ljbffr

📌 Senior Asic Verification Architect At Hcltech (Toronto)
🏢 HCL Technologies
📍 Toronto