Elevate your career as a Senior Design Lead at HCLTech, specializing in ASIC/SoC development. Bring your 5-7 years of experience and deep technical skills to a global leader.As a pivotal member of HCLTech, you will focus on ASIC/SoC life cycle management and verification processes. This role requires expertise in block-level and sub-system testbench development using SystemVerilog and UVM methodologies. Engage in functional coverage implementation and debugging using industry-standard EDA tools to ensure high-quality designs.Key Responsibilities:
- Define full chip TB architecture and verify designs
- Develop and maintain comprehensive ASIC/SoC test plans
- Execute and debug constrained-random and directed test cases
- Handle functional coverage and assertions coding effectively
- Analyze simulation data to identify and resolve issuesRequirements:
- 5 to 7 years of relevant experience
- Proficient in Verilog, SystemVerilog, and UVM
- Solid knowledge of digital logic and finite state machines
- Familiarity with simulation tools like Synopsys VCS and Cadence tools
- Basic scripting skills in Python, Tcl, or PerlDrive your impact in ASIC/SoC design with HCLTech today.#J-18808-Ljbffr

📌 Senior Asic/Soc Design Lead At Hcltech (East Gwillimbury)
🏢 HCL Technologies
📍 East Gwillimbury