? Hiring: Memory Layout Engineer 6+ Years

? Location: Ottawa, Ontario, Canada

? Work Mode: Onsite We are looking for a highly skilled Memory Layout Engineer with solid expertise in advanced-node technologies and hands-on experience in memory layout development, physical verification, and top-level integration.

? Key Responsibilities

- Custom layout development for SRAM, Register Files, ROM & TCAM
- Layout optimization for Sense Amplifiers, Control Circuits, I/O Blocks, Bit-Cell Arrays & Decoders
- Top-level memory integration within SoC environments
- Physical verification and signoff closure
- DRC, LVS & Density Checks
- IR Drop and Electromigration (EM) analysis and mitigation
- Collaborate with Circuit Design, Physical Design & Process teams

? Required Skills

- Memory Layout Design
- Advanced Node / FinFET technologies
- Hands-on experience with TSMC 7nm FinFET
- SRAM / ROM / TCAM / Register Files




- Physical Verification – DRC, LVS, Density
- IR/EM Analysis
- Top-Level Memory Integration
- Strong debugging and problem-solving skills

? Preferred

- Experience with TSMC 6nm / 5nm / 4nm / 3nm
- Strong understanding of memory architecture and layout methodologies
- Cadence Virtuoso / Calibre experience

? Education: Bachelor’s/Master’s in Electrical/Electronics Engineering or related field.

? Onsite Requirement: Candidates must be able to commute to the Ottawa, Ontario location.

? Interested candidates? DM me your updated resume.

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📌 Memory Layout Engineer (Ottawa)
🏢 Value Innovation Labs
📍 Ottawa