Astera Labs in Toronto is seeking a Technical Lead Physical Design Engineer to support the design of connectivity ASICs for cloud service providers. The role involves end-to-end STA ownership and collaboration with various teams to ensure timing convergence.
Candidates should have a Bachelor's in Electrical Engineering or Computer Science, with 5+ years of relevant experience in timing analysis and robust knowledge of physical design tools like Cadence and Synopsys. Proficiency in scripting is essential.