Bring your skills to a transformative role as a Senior Digital Design & Verification Engineer in Zurich, specializing in RTL, UVM, and microarchitecture. This role offers a unique hybrid focus within a deep-tech architecture environment.
In this senior position, you will play a crucial role in developing RTL for compute subsystems, contributing to microarchitecture standards and engaging in technical reviews. Additionally, you will construct UVM-based verification environments and assist with FPGA and silicon validation tasks, collaborating with multidisciplinary teams.
Key Responsibilities:
• Develop RTL for complex compute subsystems
• Engage in microarchitecture definitions and technical evaluations
• Build and maintain UVM verification environments




• Drive functional coverage and perform debugging tasks
• Assist with FPGA bring-up and silicon validation processes
Requirements:
• Robust RTL coding skills in SystemVerilog/Verilog
• Proficient in UVM and advanced DV methodologies
• Knowledgeable in SoC integration and communication buses
• Experience with FPGA, DFT, and verification approaches
• Strong ownership across design and verification processes
Maximize your impact and expertise as part of a pioneering team in Zurich.
#J-18808-Ljbffr

📌 Expert in Digital Design & Verification (Zurich)
🏢 Botic Partners
📍 Zurich