Altera seeks a Senior FPGA Compiler Engineer focused on routing. Make groundbreaking advancements in FPGA architecture through cutting-edge routing algorithm development.
In this significant role within Altera’s Toronto office, your responsibilities will center on optimizing FPGA routing algorithms. With over 9 years in FPGA or ASIC tools, you're expected to enhance the compiler tools that affect performance and usability of complex designs. Engaging with architecture and hardware teams, you will address challenges such as routing congestion and timing violations.
Key Responsibilities:
• Design and implement routing algorithms to boost performance
• Contribute to placement and timing optimizations within the compiler




• Enhance runtime and memory efficiency of routing systems
• Work with cross-functional teams on routing strategies
• Investigate design issues to improve algorithm convergence
Requirements:
• 9+ years in FPGA design, ASIC or EDA
• Solid command of algorithms and graph structures
• Familiarity with FPGA design processes and C/C++
• Degree in Electrical Engineering or related field
• Strong team collaboration and communication skills
Elevate your career in FPGA design and join Altera's cutting-edge team in Toronto.
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📌 Senior Engineer for FPGA Compiler Routing (Toronto)
🏢 754 Altera Semiconductor Technology (M) Sdn. Bhd.
📍 Toronto