Elevate your career as a Lead ASIC Digital Design Engineer with Synopsys, specializing in innovative High Bandwidth Memory designs. Drive advancements in digital and mixed-signal technology in a collaborative environment.
As part of our High Bandwidth Memory PHY RTL team, you will apply 7-10 years of ASIC design expertise to tackle complex challenges. Your knowledge of RTL development and physical implementation will be instrumental in product development. Mentor junior engineers and support the integration of high-quality IP into customer SoCs.
Key Responsibilities:
• Lead RTL design for cutting-edge HBM PHY IP
• Convert high-level architecture into functional RTL
• Collaborate with teams in analog and physical design




• Innovate timing closure strategies and low power techniques
• Automate verification processes to streamline workflows
Requirements:
• 7-10 years of RTL design experience
• Robust familiarity with SystemVerilog and Verilog
• Expertise in timing closure and high-speed design
• Comprehensive knowledge of ASIC development phases
• Proficiency with automation using scripting tools
Join Synopsys and leverage your digital design skills to contribute to pioneering memory interface solutions.
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📌 Lead ASIC Digital Design Engineer at Synopsys (Ottawa)
🏢 Synopsys
📍 Ottawa