Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling customers to efficiently map complex designs to cutting-edge FPGA architectures.

Position Overview

Senior FPGA Compiler Engineer (Routing) – This role focuses on the development and optimization of FPGA routing algorithms within the compiler toolchain, directly impacting performance, power, and usability of next‑generation FPGA devices.

Responsibilities

- Design, implement, and optimize FPGA routing algorithms to improve performance, routability, and timing closure.
- Contribute to the FPGA compiler flow, including placement, routing, and timing‑driven optimization.
- Analyze and enhance runtime, memory efficiency, and scalability of routing algorithms for large designs.
- Collaborate closely with architecture, synthesis, timing (STA), and hardware teams to align routing strategies with device capabilities.
- Investigate routing congestion, timing violations, and design bottlenecks; develop solutions to improve convergence.
- Integrate routing features into existing compiler infrastructure and ensure robustness across diverse customer use cases.

Qualifications – Required

- 9+ years of experience in FPGA/ASIC design tools, EDA, or related fields.
- Strong background in algorithms and data structures (graph algorithms, optimization techniques).
- Experience with FPGA or ASIC design flows (placement, routing, timing closure).
- Proficiency in C/C++ and software development best practices.
- Familiarity with routing algorithms (e.g.,



maze routing, negotiated congestion), timing‑driven design methodologies, and physical design concepts.
- Ability to analyze complex systems and develop scalable, high‑performance solutions.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- Solid communication, teamwork, and interpersonal skills.

Qualifications – Preferred

- Experience with commercial FPGA toolchains (e.g., Quartus, Vivado).
- Knowledge of FPGA architectures and interconnect fabrics.
- Familiarity with parallel/distributed computing for EDA workloads.
- Experience with scripting (Python, Tcl) for tooling and automation.
- Background in timing analysis or placement algorithms.

Compensation

Estimated Salary Range: $144.6K – $209.3K CAD. Compensation reflects the Canadian labour market and may vary based on location, experience, skills, training, and job‑specific knowledge. Base salary plus performance‑based incentive opportunities are offered.

Job Type / Location

Regular – Shift 1 (Canada). Primary location: Toronto, Ontario, Canada. Additional locations available.

Equal Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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📌 Senior FPGA Compiler (Router) Engineer (Toronto)
🏢 754 Altera Semiconductor Technology (M) Sdn. Bhd.
📍 Toronto