Altera seeks a Static Timing Analysis Skilled to advance FPGA design efforts in Toronto, Ontario. Your role will focus on executing timing analyses, resolving violations, and collaborating for optimal design outcomes.
In this key position at Altera, you will leverage your STA expertise to support timing closure for FPGA designs. The ideal candidate will possess over six years of experience in STA, a solid understanding of industry-standard tools, and the ability to work effectively within diverse engineering teams. Your responsibilities will include developing timing constraints and driving performance optimizations.
Key Responsibilities:
• Perform timing analysis, ensuring accurate setup/hold checks
• Collaborate with teams to debug timing violations




• Validate and develop timing constraints
• Work on timing convergence improvements
• Contribute to automation and methodology enhancements
Requirements:
• 6+ years of experience in STA for FPGA/ASIC
• Comprehensive knowledge of STA fundamentals
• Familiarity with synthesis and place & route
• Working knowledge of RTL design languages
• Bachelor’s or Master’s degree in relevant fields
Elevate your career in FPGA design with Altera's STA team.
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📌 Static Timing Analysis Professional (Toronto)
🏢 Altera
📍 Toronto