Digital Design & Verification (RTL + UVM + Microarchitecture)
Job Description: Senior Digital Design & Verification Engineer
We are searching for Senior Digital Engineers with strong RTL and Verification expertise to join a deep-tech compute architecture team. The role involves hybrid responsibilities across microarchitecture, RTL development, DV environments and subsystem integration.
Responsibilities
- Develop RTL for compute subsystems, controllers, datapaths and interfaces
- Contribute to microarchitecture definition and technical reviews
- Build UVM-based verification environments and test plans
- Drive functional coverage, constrained-random testing and debug
- Support FPGA bring‑up and silicon validation activities
- Collaborate with physical design, architecture and mixed-signal teams
Requirements
- Strong background in RTL coding (SystemVerilog/Verilog)
- Solid experience with UVM and up-to-date DV methodologies
- Knowledge of SoC integration, buses, protocols (AXI/APB)
- Exposure to FPGA, DFT, CDC/RDC, linting and subsystem verification
- Ability to work across design + verification flows with technical ownership