SRA Group seeks a memory layout designer for on-site work in Ottawa, Ontario. You will design and optimize memory blocks for SoC integration, addressing DV/EM issues and ensuring successful tapeouts.
Required are a degree in Electrical/Electronics Engineering and hands-on experience with memory layouts at advanced nodes, especially TSMC 7nm FinFET. Solid problem-solving and cross-team collaboration are essential.
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📌 Memory Layout Engineer: SoC Optimization & Tapeout Lead (Ottawa)
🏢 SRA Group
📍 Ottawa
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