Take charge as a Senior Verification Manager at Synopsys, where you will oversee SERDES PHY mixed

- signal verification.

Optimize your team's capabilities for high-impact silicon projects.

In this leadership role, you will manage verification staff engaged in mixed-signal design challenges.
Your expertise will be crucial in debugging complex issues, assessing coverage, and ensuring the sign-off quality of SERDES PHY IPs.

You'll play a pivotal role in cross-disciplinary engagement to close technical gaps.

Key Responsibilities:

- Lead verification efforts in mixed-signal environments using UVM
- Troubleshoot customer escalations and debug priority regressions
- Maintain rigorous standards for verification quality
- Define co-simulation methodology and standards
- Facilitate collaboration with analog and firmware teams Requirements:
- 10+ years in ASIC verification with a focus on mixed-signal
- 3+ years leading verification engineers
- Expertise in PCIe and Ethernet SERDES
- Proficient in System Verilog and verification methodologies
- Robust scripting ability using Python or Perl Contribute to cutting-edge verification processes while building a technically skilled team at Synopsys.

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📌 Senior Verification Manager with SERDES Focus (London)
🏢 Synopsys
📍 London