Digital Asic Design Engineer — Rtl, Systemverilog - C$109,000 - C$174,000 A Year (Varennes)

Digital Asic Design Engineer — Rtl, Systemverilog - C$109,000 - C$174,000 A Year (Varennes)

04 Aug
|
Ciena
|
Varennes

04 Aug

Ciena

Varennes

Seeking an experienced Digital ASIC Design Engineer for product development in high-speed connectivity solutions. Responsibilities include RTL design, debugging, and lab validation using SystemVerilog.

📌 Digital Asic Design Engineer — Rtl, Systemverilog - C$109,000 - C$174,000 A Year (Varennes)
🏢 Ciena
📍 Varennes

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