Celero Communication Inc. is an exciting and quick-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. We are seeking an experienced Physical Design Engineer to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R;), clock tree synthesis, timing closure, and physical verification.

You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products. RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs)



or complex digital blocks.

Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.

Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers Signoff & Verification: Run Static Timing Analysis (STA) and physical verification.

Fix Design Rule

Checking (DRC) and Layout Versus Schematic (LVS) violations. Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl. Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness. Must have 5+ years of relevant ASIC physical design experience (depending on degree level).

Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

📌 Senior/Principal Physical Design Engineer (Medicine Hat)
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