Advance your career with Celero Communications as a Full-Chip Physical Verification Engineer focused on cutting-edge DSP technology. Engage in the entire Physical Verification process across complex digital blocks.

Celero

Communications, Inc. seeks a Full-Chip Physical Verification Engineer to join its growing Physical Design team in San Jose, CA. This senior position involves leading the verification process across TSMC nodes, ensuring quality and manufacturability throughout multiple projects. You will enhance execution efficiency and work collaboratively with Analog Design teams to resolve verification challenges effectively. Key Responsibilities:
Lead full chip Physical Verification initiatives
Own execution plans and schedules for verification




Conduct thorough full chip and block PV checks
Analyze DRC/ERC/LUP/PERC results comprehensively
Collaborate with teams to influence floorplan and implementation strategies Requirements:
Bachelor’s or Master’s degree in Electrical Engineering
7+ years of full-chip verification experience
Proficient with ICV or Calibre verification tools
Expertise in floorplanning to mitigate DRC/LVS issues
Experience in advanced process technologies preferred Enhance your verification capabilities and drive innovations in semiconductor technology with Celero Communications.

📌 Full Chip Physical Verification Engineer At Celero Red Deer (Canada)
🏢 Socket.dev
📍 Canada