Elevate your engineering career as a Digital Design Architect with Synopsys. This hybrid or remote role focuses on high-speed Ser Des IP design, enabling cutting-edge AI-powered products.

At Synopsys, you'll leverage over 10 years of digital ASIC design experience within a energetic mixed-signal setting. Your expertise in Verilog or VHDL, clock domain crossing, and low-power architecture will be essential. As a mentor, you'll guide junior engineers and foster collaboration across teams, ensuring that your architectural decisions have lasting impacts on the performance of networking and storage products.

Key Responsibilities:
Architect digital subsystems for high-speed Ser Des IP
Define interface specifications translating system-level requirements




Lead design flow for low-power architecture decisions
Collaborate with ASIC verification engineers on testplans
Perform gate-level simulations and debug failures

Requirements:
Master's degree in Electrical Engineering or equivalent
10+ years of digital ASIC design experience
Proficiency in Verilog or VHDL
Experience with clock domain crossing methodologies
Familiarity with high-speed digital interfaces

Shape the future of high-performance connectivity with Synopsys and innovate today for a better tomorrow.
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📌 Digital Design Architect At Synopsys Markham
🏢 Synopsys
📍 Markham