SRA Group seeks a memory layout designer for on-site work in Ottawa, Ontario. You will design and optimize memory blocks for SoC integration, addressing DV/EM issues and ensuring successful tapeouts.
Required are a degree in Electrical/Electronics Engineering and hands-on experience with memory layouts at advanced nodes, especially TSMC 7nm FinFET. Robust problem-solving and cross-team collaboration are essential.
#J-18808-Ljbffr
📌 Memory Layout Engineer: SoC Optimization & Tapeout Lead (Quebec City)
🏢 SRA Group
📍 Quebec City
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.