Elevate your career as a Senior Design Lead at HCLTech, specializing in ASIC/SoC development. Bring your 5-7 years of experience and deep technical skills to a global leader.

As a pivotal member of HCLTech, you will focus on ASIC/SoC life cycle management and verification processes. This role requires expertise in block-level and sub-system testbench development using SystemVerilog and UVM methodologies. Engage in functional coverage implementation and debugging using industry-standard EDA tools to ensure high-quality designs.

Key Responsibilities:
• Define full chip TB architecture and verify designs
• Develop and maintain comprehensive ASIC/SoC test plans
• Execute and debug constrained-random and directed test cases




• Handle functional coverage and assertions coding effectively
• Analyze simulation data to identify and resolve issues

Requirements:
• 5 to 7 years of relevant experience
• Proficient in Verilog, SystemVerilog, and UVM
• Robust knowledge of digital logic and finite state machines
• Familiarity with simulation tools like Synopsys VCS and Cadence tools
• Basic scripting skills in Python, Tcl, or Perl

Drive your impact in ASIC/SoC design with HCLTech today.
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📌 Senior ASIC/SoC Design Lead at HCLTech (Ontario)
🏢 HCL Technologies
📍 Ontario