TekWissen Group has a temporary, onsite Design Engineer role in Markham, ON for 6 months. The engineer will modify RTL for Graphics Core IP blocks, adding features such as clock gating, counters, and debug support, working with senior engineers across verification and power teams.
Applicants should have robust digital design fundamentals, experience with Verilog/SystemVerilog, and scripting skills (Perl/Tcl/Python/Bash).