About O-HIVE

O-HIVE develops real-time Visual Language Model technology for robotics, industrial automation, spatial perception, and autonomous systems.

Our platform enables robots to understand visual scenes, estimate three-dimensional position and geometry, reason about objects and environments, and execute robotic tasks without requiring extensive application-specific data collection or model retraining.

O-HIVE is developing a dedicated 3D VLM robotics chip designed to combine visual perception, spatial intelligence, multimodal AI inference, and real-time robotic control in a power-effective edge computing platform.

Position Overview

O-HIVE is seeking an ASIC Chip Design Engineer to contribute to the architecture, RTL development, verification, prototyping, and implementation of a next-generation 3D Visual Language Model processor for robotics.

The engineer will work closely with O-HIVE’s AI, FPGA, embedded systems, computer vision, robotics, and semiconductor architecture teams to translate VLM and 3D perception workloads into productive hardware accelerators.

The target architecture will support mixed-precision AI inference, image and depth processing, multimodal transformer workloads, sensor synchronization, spatial reasoning, and low-latency robot control.

Key ResponsibilitiesASIC Architecture and RTL Design

- Design and implement digital ASIC blocks using Verilog or SystemVerilog.
- Translate AI, VLM, computer vision, and robotics algorithms into hardware architectures.
- Develop processing blocks for matrix multiplication, convolution, attention, normalization, activation, and tensor operations.
- Design mixed-precision compute units supporting formats such as INT8, INT4, FP16, BF16, and FP8.
- Develop memory controllers, DMA engines, buffering systems, cache structures, and on-chip interconnects.
- Contribute to Network-on-Chip architecture and dataflow optimization.
- Design interfaces between AI accelerators, image-processing pipelines, embedded CPUs, memory, sensors, and robotic control systems.
- Support scalable accelerator architectures using multiple parallel processing engines.

3D Vision and Robotics Acceleration

- Develop hardware acceleration for RGB, RGB-D, ToF, stereo vision, and 3D point-cloud processing.
- Support depth estimation, feature extraction, image preprocessing, coordinate transformation, pose estimation, and spatial mapping.
- Optimize hardware pipelines for real-time perception and robotic-control workloads.
- Develop low-latency interfaces for cameras, depth sensors, robot controllers, FPGA preprocessing systems, and industrial communication protocols.
- Support deterministic timing, timestamp synchronization, and real-time sensor fusion.
- Work with robotics engineers to maintain predictable inference and control latency.

Verification and Validation

- Develop testbenches, assertions, coverage plans, and verification environments.
- Perform functional verification at block, subsystem, and SoC levels.
- Support simulation, linting, clock-domain crossing analysis, reset-domain crossing analysis, and formal verification.
- Validate RTL implementations against Python, C++, PyTorch, or algorithmic reference models.
- Investigate performance bottlenecks, numerical accuracy issues, and hardware-software integration problems.
- Support emulation and FPGA-based prototyping before tape-out.





Synthesis and Physical-Design Collaboration

- Support RTL synthesis, timing analysis, power estimation, and area optimization.
- Work with physical-design engineers on floorplanning, clocking, power delivery, congestion, and timing closure.
- Review synthesis and place-and-route results and revise RTL as required.
- Contribute to design-for-test, scan, memory BIST, and production-test planning.
- Support foundry, IP vendor, packaging, and manufacturing-partner engagement.
- Assist with design reviews, tape-out preparation, silicon bring-up, and post-silicon validation.

Performance and Power Optimization

- Analyze workload utilization, memory bandwidth, latency, throughput, and power consumption.
- Optimize data movement between compute engines, SRAM, external memory, and sensor interfaces.
- Evaluate architecture tradeoffs involving compute density, memory capacity, bandwidth, die area, thermal limits, and manufacturing cost.
- Develop power-gating, clock-gating, and workload-scheduling strategies.
- Support chip-package-system thermal analysis for actively cooled robotics deployments.

Cross-Functional Development

- Collaborate with AI researchers to profile VLM, transformer, vision, and 3D perception workloads.
- Work with compiler and software engineers to define operators, instruction sets, runtime APIs, and hardware abstraction layers.
- Coordinate with FPGA engineers to prototype and validate accelerator blocks.
- Work with embedded engineers on boot, firmware, drivers, diagnostics, and hardware control.
- Participate in architecture reviews, design documentation, performance modeling, and technical roadmap planning.

Required Qualifications

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience in digital logic design and ASIC development.
- Strong proficiency in Verilog or SystemVerilog.
- Understanding of synchronous digital design, pipelining, finite-state machines, clock-domain crossing, and reset design.
- Experience with simulation, linting, synthesis, static timing analysis, or formal verification tools.
- Understanding of ASIC design flow from specification through RTL, verification, synthesis, physical design, and tape-out.
- Knowledge of processor, accelerator, memory, interconnect, or SoC architecture.
- Strong debugging, documentation, and problem-solving skills.
- Ability to work effectively across semiconductor, AI, robotics, and embedded-system teams.

Preferred Qualifications

- Experience designing AI, machine-learning, computer-vision, or transformer accelerators.
- Experience with matrix multiplication engines, systolic arrays, vector processors, SIMD architectures, or custom tensor-processing units.
- Knowledge of transformer operations, including attention, KV cache, normalization, quantization, and multimodal inference.
- Experience with FP8, BF16, FP16, INT8, INT4, or mixed-precision arithmetic.




- Experience with image-signal processing, depth processing, point clouds, SLAM, pose estimation, or sensor fusion.
- Experience with FPGA prototyping using AMD/Xilinx, Intel, or similar platforms.
- Familiarity with AMBA AXI, PCIe, MIPI CSI-2, Ethernet, LPDDR, DDR, HBM, SPI, I²C, UART, or industrial interfaces.
- Familiarity with RISC-V, ARM-based SoCs, embedded CPUs, or custom instruction-set extensions.
- Experience with EDA tools from Synopsys, Cadence, Siemens EDA, or equivalent vendors.
- Knowledge of DFT, scan insertion, ATPG, MBIST, or silicon-test methodologies.
- Experience with advanced-node or mature-node semiconductor processes.
- Experience with silicon bring-up, evaluation boards, laboratory equipment, or post-silicon debugging.
- Familiarity with Python, C, C++, PyTorch, ONNX, CUDA, HLS, or hardware performance modeling.
- Experience working with foundries, semiconductor IP providers, packaging companies, or outsourced design partners.

Example Development Areas

The successful candidate may contribute to one or more of the following:

- Mixed-precision VLM inference accelerator
- Transformer attention and matrix-processing engine
- 3D vision and spatial-computing accelerator
- RGB-D and ToF sensor-processing pipeline
- On-chip SRAM and memory-bandwidth architecture
- Multicore AI accelerator and Network-on-Chip
- Sensor synchronization and timestamp-processing subsystem
- Embedded RISC-V or ARM control subsystem
- FPGA prototype of the O-HIVE VLM architecture
- Robotics safety, diagnostics, and real-time control interfaces
- Power-management and thermal-monitoring architecture
- Post-silicon validation and performance characterization

Ideal Candidate

The ideal candidate combines strong digital-design fundamentals with an interest in AI acceleration, computer vision, and robotics.

You should be comfortable working in an early-stage development environment where hardware architecture, AI models, software tools, and system requirements are developed together. You should be able to move between high-level workload analysis and detailed RTL implementation while clearly documenting engineering assumptions, tradeoffs, and results.

Why Join O-HIVE

- Develop a new semiconductor architecture specifically designed for real-time 3D VLM robotics.
- Work at the intersection of ASIC design, multimodal AI, computer vision, spatial computing, and robotic control.
- Contribute to the complete product lifecycle, including architecture, FPGA prototyping, tape-out, silicon bring-up, and deployment.
- Collaborate with experienced semiconductor, robotics, AI, and industrial-automation leaders.
- Help build foundational computing technology for industrial robots, humanoid robots, autonomous systems, and next-generation intelligent machines.

Application

Please submit the following:

- Resume or curriculum vitae
- Brief description of relevant ASIC, FPGA, SoC, AI-accelerator, or processor-design experience
- Examples of RTL modules, chip projects, technical publications, patents, or open-source contributions, where available
- Your preferred work location and availability

O-HIVE Inc. is an equal-opportunity employer. We evaluate candidates based on their skills, experience, technical potential, and ability to contribute to our mission.

Pay: $60,000.00-$100,000.00 per year

Work Location: In person

📌 ASIC Chip Design Engineer (3D Visual Language Model Robotics Chip Development) (401)
🏢 O-HIVE
📍 401