Elevate your career as a Senior Analog Designer, specializing in SERDES and memory PHY support. Provide crucial evaluations that guarantee high-performance IP functionality.
This role emphasizes pre-silicon and post-silicon support, where you'll evaluate electrical aspects like power, signal, and clock integrity. Your expertise will also assist post-silicon teams in screening and testing third-party IP to ensure compliance and functionality. Previous experience with SERDES or memory PHY designs is essential for this position.
Key Responsibilities:
• Evaluate electrical integrity for SERDES IP efficiently
• Support teams during both pre-silicon and post-silicon phases
• Conduct compliance testing and characterization for third-party IP




• Monitor and analyze clock distribution metrics such as jitter
• Apply basic signal integrity concepts in evaluations
Requirements:
• Proven background in SERDES or memory PHY designs
• Knowledge of power noise production issues
• Familiarity with signal integrity fundamentals
• Solid grasp of characteristic and termination impedance
• Experience in clock distribution metrics like DCD
Utilize your technical skills to enhance SERDES and memory PHY designs.
J-18808-Ljbffr

📌 Analog Designer: Serdes & Memory Phy Markham
🏢 Infotree Global Solutions
📍 Markham