Role Overview Design and implement custom layouts for memory blocks, including:
Develop and optimize layouts for critical memory components such as:
Perform top-level memory integration, ensuring seamless assembly of memory macros within SoC environments
Execute and resolve physical verification checks, including:
Density checks
Drive layout cleanup and signoff closure, ensuring high-quality tapeout readiness
Analyze and mitigate IR drop and EM (Electromigration) issues in memory layouts
Collaborate with circuit design, physical design, and process teams to ensure optimal performance, area, and power
Required Qualifications Bachelor’s/Master’s degree in Electrical/Electronics Engineering or related field
Proven experience in memory layout design at advanced technology nodes
Hands-on experience with TSMC 7nm FinFET technology




Preferred Qualifications Experience with TSMC 6nm / 5nm / 4nm / 3nm technologies
Solid understanding of memory architecture and layout methodologies
Familiarity with industry-standard layout and verification tools (e.g., Virtuoso, Calibre)
Key Skills Physical verification (DRC, LVS, Density)
IR/EM analysis and mitigation
Top-level memory integration
Strong problem-solving and debugging skills
This role is considered an on-site position located in Ottawa, Ontario, CANADA
You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours

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📌 Memory Layout Engineer (Quebec City)
🏢 SRA Group
📍 Quebec City