Lead or contribute to verification of 4–5 ASIC design blocks.
Develop UVM-based verification environments, sequences, tests, debug, and coverage closure.
Solid experience in SystemVerilog/UVM.
Experience with PCIe, UCIe 2.0, and Ethernet protocols.
Ability to independently own verification deliverables.
Support customer collaboration in EST timezone.
Required Skills
Strong SystemVerilog/UVM verification experience
Knowledge and/or hands-on experience with:
UCIe 2.0
PCIe
Ethernet
Ability to own design blocks independently and drive verification closure
Responsibilities
The DV team is expected to:
Own verification of 4–5 design blocks per ASIC
Develop and execute sequences
Perform test development and debug
Drive coverage collection and closure
Own end-to-end verification execution for assigned blocks
The customer will own the testbench infrastructure.
Key Responsibilities
1.
To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations, contributing to the creation of seamless user experiences.
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.