Job TitleDebug Sub-System & Design-for-Test (DFT) EngineerSummaryWe are seeking a Debug Sub-System / DFT Engineer to architect, implement, and validate the on-chip debug and test infrastructure for complex SoC and ASIC designs. This role spans the full lifecycle — from specification and RTL design of debug/DFT features through pre-silicon verification, ATPG pattern generation, and post-silicon validation. The ideal candidate combines deep DFT methodology expertise with knowledge of silicon debug subsystems, enabling efficient manufacturing test, in-field diagnostics, and post-silicon debug.Key ResponsibilitiesDebug Sub-System Design & IntegrationUnderstanding of on-chip debug infrastructure including:JTAG TAP controllers (IEEE 1149.1/1149.6) and daisy-chain/star topologiesCoreSight / ARM Debug Architecture (DAP, SWD, ETM, CTI, cross-trigger matrices)Trace infrastructure (ETB, ETR, TPIU, trace funnels, timestamps)Embedded Logic Analyzers (ELA) / on-chip signal monitorsDebug authentication and security (secure debug, debug access levels, lock/unlock)Design and integrate DFx (Design for Debug/Diagnostics) features:Performance counters and event monitorsError logging and first-error capture registersSignal observation via debug muxes and pad multiplexingRegister access over debug ports (JTAG-to-APB/AHB/AXI bridges)Debug subsystem interconnect (debug bus, cross-trigger fabric, power-domain-aware debug access)Collaborate with architecture teams on debug use cases: boot debug, crash analysis, performance profiling, in-field diagnosticsDesign-for-Test (DFT)Understand DFT architecture for complex SoC designs, including:Scan insertion: full scan, compressed scan (Tessent, Modus, DFT Compiler)Memory BIST (MBIST): controller design, repair logic, redundancy allocationLogic BIST (LBIST): self-test controllers, PRPG, MISR, fault coverage analysisBoundary Scan (JTAG): BSR chain design, IEEE 1149.1 complianceAt-speed testing: launch-on-shift, launch-on-capture, multi-clock domain handlingDrive ATPG pattern generation and achieve target fault coverage (stuck-at, transition,



path delay, bridging)Implement test compression (DFTMAX, Tessent TestKompress, EDT) to reduce test data volume and ATE test timeDesign DFT for low-power: isolation, retention scan, UPF-aware DFT insertionHandle analog/mixed-signal test interfaces (ADC/DAC BIST, PLL test modes, SerDes loopback)Define and implement test access mechanisms (TAM): wrapper chains, hierarchical test, IEEE 1500 wrappers for IP coresVerification & Validation (Most Key)Verify DFT/debug RTL through simulation and formal methods:JTAG TAP compliance testsScan chain integrity checksMBIST/LBIST functional verificationDebug authentication sequence validationRun DRC (Design Rule Checks) for DFT: scan rule violations, clock gating, X-sources, hold-time fixesPerform ATPG dry runs and iterate on coverage closure with design teamsSupport post-silicon DFT validation: scan pattern bring-up, MBIST execution, yield debugDebug test escapes and drive corrective actions (pattern update, DFT ECO, coverage gap closure)Manufacturing Test & YieldCollaborate with test engineering and ATE teams on test program developmentOptimize test cost: pattern count, test time, multi-site efficiency, compression ratioSupport yield analysis and diagnosis: failing pattern debug, defect localization, systematic vs. random fail classificationDevelop and maintain DFT documentation: test architecture specs, coverage reports, test insertion guidelinesRequired QualificationsEducation: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related fieldExperience: 4–10+ years in DFT, debug subsystem design, or silicon test engineeringStrong expertise in one or both domains:Proficiency in RTL design using Verilog/SystemVerilogExperience with industry DFT tools:Knowledge of JTAG/IEEE 1149.1 standard and TAP controller state machineExperience with ATPG pattern generation, fault models (SA0/SA1, transition, IDDQ), and coverage analysisFamiliarity with memory test (March algorithms, repair, redundancy, fuse programming)Strong scripting skills: Tcl, Python, Perl for tool automation and flow developmentUnderstanding of SoC integration and multi-IP DFT challenges

📌 Design For Test (Dft) Engineer (New Glasgow)
🏢 HCLTech
📍 New Glasgow