Elevate your career at Synopsys as a Senior Manager in ASIC digital design and verification. Spearhead development initiatives that drive innovation in AI-powered systems. As a key player at Synopsys, you will manage a team of verification engineers focusing on SERDES PHY.

With over ten years in mixed-signal verification, your technical expertise will guide developers through complex debug processes and ensure high-quality product releases. You’ll be instrumental in enhancing verification methodologies while fostering the growth of your team members. Key Responsibilities:
Lead distributed verification teams on SERDES PHY projects
Directly debug silicon correlation and regressions
Ensure that verification meets high sign-off standards




Develop and refine verification methodologies using UVM
Collaborate closely with firmware and design teams Requirements:
10+ years experience in ASIC mixed-signal verification
Proven leadership in managing teams and projects
Solid understanding of PCIe and Ethernet designs
Mastery in SystemVerilog and UVM, including test plans
Scripting abilities in Python or Shell Make a significant impact in the field of mixed-signal verification at Synopsys, where your leadership will drive future innovations.

📌 Senior Asic Digital Design Manager At Synopsys Mississauga
🏢 Synopsys
📍 Mississauga