Explore a pivotal role as a Memory Layout Engineer where you'll leverage hands-on experience with SRAM and vital memory building blocks. Join us to refine your skills on advanced FinFET processes.
In this position, you will engage with critical aspects of memory layout, including control, sense amplifiers, and decoders. Ideal candidates will have experience working with at least 7nm FinFET technologies, with 6nm or below being highly beneficial. You'll be responsible for top-level memory integration and ensuring design rule checks (DRC), layout versus schematic checks (LVS), and density verifications across various memory elements.
Key Responsibilities:
• Develop and verify layouts for SRAM and ROM memory blocks
• Ensure integration and verification of physical memory configurations
• Address IR/EM issues effectively within layouts
• Perform DRC and LVS checks on memory designs
• Clean and verify physicals to meet specifications
Requirements:
• Hands-on experience with 7nm FinFET processes
• Familiarity with memory layout tools and techniques
• Knowledge of IR/EM related layout challenges
• Experience with top-level memory integration processes
• Robust understanding of DRC and LVS verification processes
This role allows you to showcase your expertise in memory layout design and integration.
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