Harness innovation at Microchip Technology as a Principal RTL Design Engineer. This pivotal role involves designing high-performance analog and mixed-signal circuits, requiring expertise in RTL design and verification.
In the Mixed Signal Development Group, your contributions will enhance various divisions. You’ll collaborate with talented engineers throughout the ASIC development lifecycle and utilize advanced CMOS processes. Proficiency in Verilog/SystemVerilog is necessary, alongside a passion for developing cutting-edge integrated circuits for wireline applications.
Key Responsibilities:
• Oversee complete ASIC design from verification to debugging
• Implement RTL designs using Verilog/SystemVerilog and integrate blocks
• Perform simulations, lint checks, and run CDC analysis




• Work with cross-functional teams on timing closure and debugging
• Create high-quality documentation for design and testing
Requirements:
• Bachelor’s/Master’s/PhD in Electrical/Computer Engineering
• 2-10 years of relevant ASIC development experience
• Experience in RTL design and verification required
• Familiarity with lab debugging equipment
• Knowledge of C/C++ and scripting languages advantageous
Leverage your RTL design expertise to contribute to transformative projects at Microchip.
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📌 Principal Engineer RTL Design Role (Burnaby)
🏢 Microchip Technology
📍 Burnaby