Elevate your expertise with Synopsys as a Senior Analog Layout Design Engineer, focusing on robust layout design and methodology. Utilize tools like Custom Compiler SDL or Virtuoso XL to enhance productivity and innovation.
In this role, you will optimize analog mixed signal layouts, leveraging your 5+ years of experience in risk management, device matching, and physical verification. Your collaboration with global teams will support the development of innovative designs while reducing iterations and improving yield, with a solid emphasis on documentation and automation.
Key Responsibilities:
• Develop and optimize analog mixed signal layouts with precision
• Oversee macro floor planning and ensure layout integrity
• Address DRC, LVS, Antenna, DFM checks effectively
• Implement PERC verification for ESD and latch-up management
• Collaborate globally to standardize processes and best practices
Requirements:
• Degree in Electrical Engineering or a related field
• 5+ years of relevant layout design experience
• Solid skills in Custom Compiler SDL or Virtuoso XL
• Comprehensive understanding of verification processes
• Experience in scripting, preferably TCL, Perl, or Python
Shape the future of silicon design through innovative layout methodologies at Synopsys.
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