We have Memory Layout Engineer role with us
Hands-on experience with SRAM, register files, ROM, TCAM layouts of key memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc.
Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage .
Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory.
Valuable hold on IR/EM related issues in memory layouts.
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📌 Memory Layout Engineer Quebec City
🏢 Apetan Consulting
📍 Quebec City
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