Take your career to the next level as a Digital Verification Engineer with Ciena. Focus on the simulation and validation of Forward Error Correction features in innovative ASICs.

As a key part of Ciena’s technology development team, you will work closely with digital design engineers and verification architects. The Digital Verification Engineer role involves crafting comprehensive verification strategies while ensuring that the WaveLogic family of ASICs meets future communication needs. You will utilize your programming expertise in System Verilog, C++, and UVM to develop self-checking testbench environments.

Key Responsibilities:
• Read functional requirements and architectural specifications
• Collaborate closely with engineers and architects on verification tasks




• Validate FEC blocks using comprehensive simulation methods
• Develop coverage and verification test plans
• Create simulation environments with System Verilog and UVM

Requirements:
• Bachelor’s degree in Electrical/Computer Engineering or Computer Science
• Strong skills in object-oriented programming (C/C++, SystemVerilog)
• Highly detail-oriented and quality-focused
• Solid analytical and problem-solving capabilities
• Commitment to continuous learning and knowledge sharing

Join Ciena and contribute to cutting-edge network innovations through your engineering expertise.
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📌 Join Ciena as a Digital Verification Engineer (Quebec City)
🏢 Ciena
📍 Quebec City