A global semiconductor leader seeks a seasoned engineering leader to advance analog and mixed-signal IP development. You will define methodologies, enhance workflow, and provide technical leadership to ensure high-quality design outcomes. With over 5 years of experience required, candidates should have expertise in analog/mixed-signal layout and familiarity with industry tools like Synopsys Custom Compiler and Cadence Virtuoso.
Youll mentor junior engineers while collaborating with interdisciplinary teams to drive creative solutions in a rapid-paced setting.