Elevate your career with Microchip Technology as a Principal RTL Design Engineer. This role focuses on RTL design and verification in a dynamic team, driving innovation in high-performance analog and mixed-signal IP.
Join Microchip's Mixed Signal Development Group where collaboration is key. You will engage in the full ASIC design cycle, integrating IP blocks and ensuring seamless connectivity for various applications. Strong Verilog/System Verilog skills and experience working on flash controllers or DDR subsystems are essential for this position.
Key Responsibilities:
- Participate in the ASIC design lifecycle, from design to debugging
- Design RTL with Verilog/System Verilog; integrate IP blocks
- Conduct CDC analysis, simulations, and design reviews
- Collaborate with backend teams for timing closure and analysis
- Develop C-based drivers for DDR/Flash PHY and support
Requirements:
- Bachelor’s/Master’s/PhD in Engineering or related field
- 2-10 years of ASIC development experience required
- Strong RTL design skills in Verilog/System Verilog
- Hands-on debugging experience with lab equipment
- Experience in C/C++ and scripting languages a plus
Contribute your expertise in RTL design and verification to empower creative solutions at Microchip.