We are looking for an experienced Technology Lead – Memory Layout to design and develop high-performance custom memory layouts for advanced semiconductor technologies. The ideal candidate should have solid expertise in memory layout design, physical verification, FinFET technologies, and memory architectures.

Key Responsibilities:
Design and develop custom memory layouts and memory leaf cell libraries from scratch.
Optimize layouts for performance, power, and area (PPA).
Work on various memory architectures and top-level layout integration.
Perform physical verification (DRC, LVS, ERC) and resolve layout issues.
Develop layouts using Cadence Virtuoso and verify designs with Calibre .




Collaborate with cross-functional teams to ensure high-quality and timely project delivery.

Required Qualifications:
Bachelor's degree in engineering or equivalent experience.
5+ years of experience in compiler/custom memory layout design.
Hands-on experience with memory leaf cell layout development.
Robust knowledge of memory architectures and FinFET technology (3nm/5nm).
Experience with DRC, LVS, ERC, boundary conditions, Cadence Virtuoso, and Calibre.
Strong problem-solving, communication, and teamwork skills.
Must be willing to work in office in Vancouver, BC or relocate.
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📌 Memory Layout Design Engineer Vancouver (Canada)
🏢 K&K Global Talent Solutions
📍 Canada