Advance your career as a Technology Lead – Memory Layout, designing custom memory layouts for cutting-edge semiconductor technologies. Bring your expertise in FinFET technologies and memory architectures to a vibrant team in Vancouver, BC.

This position focuses on developing high-performance memory layouts from scratch and optimizing them for performance, power, and area (PPA). With over five years of experience required, you will work closely with cross-functional teams and ensure timely project delivery while performing physical verification and resolving layout issues.

Key Responsibilities: • Design custom memory layouts and libraries from the ground up • Optimize layouts for performance, power, and area (PPA)



• Integrate various memory architectures into top-level layouts • Conduct physical verification and resolve DRC, LVS, and ERC issues • Utilize Cadence Virtuoso for layout development and Calibre for verification

Requirements: • Bachelor's degree in engineering or equivalent experience • 5+ years in compiler/custom memory layout design • Proficient in memory architectures and FinFET technologies • Experience with Cadence Virtuoso and Calibre tools • Solid problem-solving and communication skills

Leverage your memory design expertise and team-oriented skills in a agile role focused on semiconductor advancements. #J-18808-Ljbffr

📌 Technology Lead – Memory Layout Engineer Winnipeg
🏢 K&K Global Talent Solutions
📍 Winnipeg