Join Cisco’s cutting-edge Common Hardware Group as an ASIC Physical Design Technical Leader, focusing on fullchip floorplans and cutting-edge design methodologies. Collaborate across teams to shape AI-era hardware solutions.

With over 8 years of experience, you will lead fullchip physical design efforts at Cisco. Your role includes collaboration on system requirements, implementing hierarchical designs, and leveraging advanced EDA tools. You will focus on RTL-to-GDSII implementation emphasizing performance, power integrity, and design optimization.

Key Responsibilities: • Design fullchip floorplans and power grids • Collaborate on package and system design requirements • Implement hierarchical design flows using EDA tools • Optimize clock mesh and static timing analysis • Analyze tool flows and improve methodologies

Requirements: • 8+ years of Physical Design experience • Proficiency with RTL-to-GDSII flow • Experience in 7nm/5nm/3nm or lower processes • Familiarity with EDA tools like Innovus and PrimeTime • Knowledge of low-power design methodologies

Lead cutting-edge ASIC designs for Cisco's transformative AI hardware platforms. #J-18808-Ljbffr

📌 Technical Leader In Asic Physical Design Vancouver
🏢 Cisco Systems
📍 Vancouver