- Support pre-silicon integration and post-silicon support of SERDES PHY IP.
- Support electrical analyses for power, signal, and clock integrity to ensure that SERDES IP operates successfully across many CLIENT SoC environments.
- Support post-silicon teams for production screening, characterization, compliance, and functional testing of 3rd Party IP.
- SERDES or memory PHY design experience of some kind.
- Understanding of power noise generation and sensitivity.
- Understanding of the basics of signal integrity, specifically termination impedance, characteristic impedance, transmission lines.
- Knowledge of clock distribution and clock specifications like jitter, DCD, etc. a plus.
- Some lab experience from functional validation or electrical testing/compliance of SERDES PHYs.