Transform FPGA design verification in this Experienced FPGA Verification Engineer role, utilizing SystemVerilog and UVM methodologies proficiently. Your expertise will drive coverage-closed, verified designs.In this position, you'll leverage over 5 years of FPGA or ASIC verification experience to develop and maintain robust verification environments. Collaboration with design teams will be essential for creating effective test plans and debugging simulation challenges. Your analytical skills will help ensure high-quality outputs from complex FPGA-based systems.Key Responsibilities:
Conduct verification of FPGA systems incorporating custom logic
Develop verification settings following UVM methodologies
Execute test plans and manage testbenches effectively




Debug simulation issues and identify root causes
Engage with design engineers for high-quality resultsRequirements:
Minimum 5 years in FPGA or ASIC verification
Robust knowledge of Verilog/SystemVerilog and hardware concepts
Hands-on experience with UVM methodologies
Familiarity with key simulation tools like in Questa or Xcelium
Scripting experience in Python or Perl is advantageousUtilize your skills in verification and FPGA systems to contribute to high-performance projects in this essential engineering role.#J-18808-Ljbffr

📌 Experienced Fpga Verification Engineer Riviere Des Prairies—pointe Aux Trembles (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 BTA Design Services
📍 Riviere-des-Prairies—Pointe-aux-Trembles