Overview: Tek

Wissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide.

This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing.

The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

Position: ASIC/RTL Design Engineer IV Location: Markham, ON L3T 7X6 Duration: 6 Months Job Type: Temporary Assignment Work Type: Onsite Job Description: THE ROLE: As a Design Engineer, you will modify and extend existing RTL for Graphics Core IP blocks.

The work willfocus on targeted feature additions, cleanup, and quality improvements such as medium-grain clock gating, performance counters, debug bus support, simple control/status logic, and related integration updates.

You will work closely with senior design engineers, architects, verification, physical design, and power teams to deliver correct, reviewable RTL changes that integrate cleanly into the broader GPU design. THE PERSON: The ideal candidate has strong digital design fundamentals, is comfortable reading and modifying existing Verilog/System

Verilog code, and can debug issues methodically.

They should be detail-oriented,collaborative, and able to take ownership of well-defined design tasks while asking positive questions when requirements or design intent are unclear. KEY RESPONSIBILITIES:



Understand relevant architecture and micro-architecture specifications for assigned Graphics Core IP blocks Modify existing RTL to implement targeted features such as clock gating, performance counters,debug bus support, and simple control/status logic Write clean, maintainable Verilog/System

Verilog and update related assertions or checks where needed Debug simulation failures, review waveforms, and work with verification engineers to close issues Collaborate with design, verification, physical design, and power teams to ensure changes meet functional, timing, power, and integration requirements Public REQUIREMENTS: Solid understanding of digital design and computer architecture fundamentals Hands-on experience with Verilog or System

Verilog RTL design Ability to read, modify, debug, and maintain existing design code Familiarity with simulation and debug tools such as VCS, Model

Sim, Verdi, waveform viewers, or equivalent tools Basic scripting ability in Perl, Tcl, Python, Bash, C-shell, or similar Solid analytical skills, attention to detail, and clear written and verbal communication GROWTH OPPORTUNITIES: Gain hands-on experience in GPU RTL design and integration Build practical expertise in Verilog/System

Verilog, simulation debug, assertions, and designquality practices Learn how performance, power, timing, and debug requirements are implemented in production GPU designs Work with experienced engineers and industry-standard design and verification tools ACADEMIC CREDENTIALS: Bachelor''s Degree in Computer, Electrical, Mechatronics Engineering or Engineering Science or similar Tek

Wissen Group is an equal opportunity employer supporting workforce diversity.

📌 ASIC/RTL Design Engineer IV (Markham)
🏢 TekWissen
📍 Markham