30 Jul
|
Cisco Systems
|
Vancouver
30 Jul
Cisco Systems
Vancouver
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
The Common Hardware
Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development from design to qualification to production is within our team, we're able to think differently, experiment more, and work quickly.
Join us to power the future of the digital world.
Fullchip
Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization. Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology. Proficiency in low-power design methodologies using UPF Experience in using AI tools to improve productivity Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical Engineering with 3+ years of Physical Design experience.
Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience in Fullchip floor-planning and power grid planning.
Experience with custom clock (H-Tree or Mesh) at chip level.
Experience with Python and usage of AI tools by giving accurate prompts At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. The starting salary range posted for this position is $142,000.00 to $181,600.00 and reflects the projected salary range for current hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training.
S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.
Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
S. employees are eligible for paid time away as described below, subject to Cisco's policies: ~10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees ~1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco ~ Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees ~ Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) ~80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours ofunused sick timecarried forwardfrom one calendar yearto the next ~ For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. #
📌 Quality Floor Lead (Vancouver)
🏢 Cisco Systems
📍 Vancouver