09 Jul
|
Celero Communication
|
Vancouver
09 Jul
Celero Communication
Vancouver
ASIC Design Engineer – Staff (Vancouver) Celero Communication seeks an ASIC Design Engineer for optical transceivers. The role focuses on digital circuit design, synthesis, timing analysis, simulation, and performance optimization using Verilog/SystemVerilog.
Responsibilities
Design, implement, and verify digital ASIC blocks for optical transceivers.
Perform synthesis, place‑and‑route, timing analysis, and simulation to meet performance targets.
Optimize designs for power, area, and speed based on project specifications.
Collaborate with cross‑functional teams to integrate ASICs into system designs.
Qualifications
Robust experience with Verilog / SystemVerilog and ASIC synthesis flow.
Proven skill in timing analysis, simulation, and optimization.
Good understanding of optical transceiver architectures.
Location: Vancouver, WA.
Equal Opportunity Employer. All qualified applicants are encouraged to apply.
📌 Asic Design Engineer - Staff (Vancouver)
🏢 Celero Communication
📍 Vancouver