ASIC Digital Verification Engineer (Ottawa)

ASIC Digital Verification Engineer (Ottawa)

19 Apr
|
Synopsys
|
Ottawa

19 Apr

Synopsys

Ottawa

Drive cutting-edge HBM products as a skilled ASIC Verification Engineer. Lead comprehensive verification plans using advanced methodologies like SystemVerilog and UVM to ensure high-quality silicon designs.
This senior role requires expertise in digital design and verification with over 10 years of experience. You will develop and execute verification strategies, automate processes with scripting languages, and collaborate with cross-functional teams to debug complex issues. A passion for innovation and a commitment to excellence are essential.
Key Responsibilities:
• Develop and execute verification plans for ASIC designs
• Write advanced test cases using SystemVerilog and UVM
• Debug complex testbench and design-related issues




• Automate verification processes with Python or Perl
• Mentor junior engineers and share best practices
Requirements:
• Bachelor’s or Master’s in Electrical Engineering
• 10+ years in digital design/verification
• Proven skills in SystemVerilog and UVM
• Solid debugging capabilities in testbench environments
• Excellent organizational and communication skills
Contribute to high-performance solutions by enhancing verification methodologies and driving continuous improvement in engineering processes.
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📌 ASIC Digital Verification Engineer (Ottawa)
🏢 Synopsys
📍 Ottawa

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