Apply on Kit Job: kitjob.ca/job/2g8zqe

Lead the development of groundbreaking security subsystems as a Senior Front-End ASIC Engineer. Focus on robust RTL implementations and drive enhancements in power, performance, and area (PPA).

This pivotal role involves architecting advanced SoC platforms and refining front-end design methodologies. Your leadership will guide a talented team in achieving design excellence and timing closure. Through collaboration and mentorship, ensure adherence to high standards in RTL quality and design verification.

Key Responsibilities: • Develop RTL using SystemVerilog/Verilog • Conduct microarchitecture definition and analysis • Ensure timing and synthesis compliance • Manage rigorous structural verification processes • Lead optimization of low-power designs

Requirements: • Deep expertise in ASIC full design flow • Experience with front-end design methodologies • Competence in analyzing design PPA • Familiarity with scripting automation tools • Knowledgeable in SoC architecture concepts

Elevate cutting-edge SoC design with your extensive ASIC knowledge and enjoy a collaborative team workplace that fosters innovation. #J-18808-Ljbffr

Apply on Kit Job: kitjob.ca/job/2g8zqe

📌 Senior Front-End ASIC Engineer for SoC Design and Optimization (Toronto)
🏢 Arm
📍 Toronto