Digital ASIC Design Engineer — RTL, SystemVerilog (Ottawa)

Digital ASIC Design Engineer — RTL, SystemVerilog (Ottawa)

19 Apr
|
Ciena
|
Ottawa

19 Apr

Ciena

Ottawa

A leading technology firm in Ottawa is seeking a Digital ASIC Design Engineer to contribute to cutting-edge product designs for high-speed connectivity solutions. This role involves collaboration on functional blocks with responsibilities in code creation, debugging, and lab validation. Candidates should have a degree in electrical or computer engineering, proficiency in System Verilog, and a team-oriented approach. The position offers an annual salary range of CAD 109,000 - CAD 174,000 alongside a comprehensive benefits package.
#J-18808-Ljbffr

📌 Digital ASIC Design Engineer — RTL, SystemVerilog (Ottawa)
🏢 Ciena
📍 Ottawa

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Plant Inspector (Ottawa)

Plant Inspector (Ottawa)

06 May
|
Hydro Ottawa
|
Ottawa
  • 06 May
  • Hydro Ottawa
  • Ottawa

Please Note: If you are a current Hydro Ottawa employee with access to Workday, apply to this job via the Workday application. At Hydro Ottawa, we power the lives of the people in the communities w [...]

Community Engagement Advisor (Ottawa)

Community Engagement Advisor (Ottawa)

07 May
|
Hydro Ottawa
|
Ottawa
  • 07 May
  • Hydro Ottawa
  • Ottawa

Please Note: If you are a current Hydro Ottawa employee with access to Workday, apply to this job via the Workday application. At Hydro Ottawa, we empower the lives of the people in the communities [...]

Subscribe to this job alert:
Enter Your E-mail address to receive the latest job offers for: digital asic design engineer — rtl, systemverilog (ottawa) / ottawa

Tenure-track faculty position in financial accounting (Ottawa)

Tenure-track faculty position in financial accounting (Ottawa)

06 May
|
University of Ottawa
|
Ottawa
  • 06 May
  • University of Ottawa
  • Ottawa

Posting Reason: New Position Job Family: Academic Leadership and Faculty Union affiliation: APUO Faculty/Department: Telfer School of Management_FT Campus: Main Campus Date Posted (YYYY/MM/DD): 2025/0 [...]

Professor in Real Estate Finance (Ottawa)

Professor in Real Estate Finance (Ottawa)

06 May
|
University of Ottawa
|
Ottawa
  • 06 May
  • University of Ottawa
  • Ottawa

Job Family: Academic Leadership and Faculty Union affiliation: APUO Faculty/Department: Telfer School of Management_FT Campus: Main Campus Date Posted (YYYY/MM/DD): 2025/09/03 Applications must be rec [...]

Subscribe to this job alert:
Enter Your E-mail address to receive the latest job offers for: digital asic design engineer — rtl, systemverilog (ottawa) / ottawa